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Freescale Semiconductor Advance Information
Document Number: MPC17510 Rev. 3.0, 1/2007
1.2 A 15 V H-Bridge Motor Driver IC
The 17510 is a monolithic H-Bridge designed to be used in portable electronic applications such as digital and SLR cameras to control small DC motors. The 17510 can operate efficiently with supply voltages as low as 2.0 V to as high as 15 V. Its low RDS(ON) H-Bridge output MOSFETs (0.45 typical) can provide continuous motor drive currents of 1.2 A and handle peak currents up to 3.8 A. It is easily interfaced to lowcost MCUs via parallel 5.0 V compatible logic. The device can be pulse width modulated (PWM-ed) at up to 200 kHz. This device contains an integrated charge pump and level shifter (for gate drive voltages), integrated shoot-through current protection (cross-conduction suppression logic and timing), and undervoltage detection and shutdown circuitry. The 17510 has four operating modes: Forward, Reverse, Brake, and Tri-Stated (High Impedance). Features * * * * * * * * 2.0 V to 15 V Continuous Operation Output Current 1.2 A (DC), 3.8 A (Peak) 450 m RDS(ON) H-Bridge MOSFETs 5.0 V TTL- / CMOS-Compatible Inputs PWM Frequencies up to 200 kHz Undervoltage Shutdown Cross-Conduction Suppression Pb-Free Packaging Designated by Suffix Code EJ
Device MPC17510EJ/R2 MPC17510MTB MPC17510MTBEL
17510
H-BRIDGE MOTOR DRIVER
MTB SUFFIX EJ SUFFIX (Pb-FREE) 98ASH70455A 24-LEAD TSSOP
ORDERING INFORMATION
Temperature Range (TA) Package
-30C to 65C
24 TSSOPW
5.0 V
15 V
17510 VDD VM C1L GOUT C1H C2L C2H CRES OUT1 EN GIN IN1 IN2
MOTOR
MCU
OUT2 GND
Figure 1. 17510 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2007. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
C2H
C2L
C1H
C1L
TOUT
14 3
13
11
12
15
CRES
Charge Pump
21 VM1 8
VDD VM2
23
Low Voltage Detector
1 5
Level Shifter Predriver H-Bridge
OUTA OUTA'
IN1 IN2
9 10
Control Logic
17 OUTB' 18 OUTB
EN TINB
16 24 6
PGND1
LGND
2 4 7 20 22
NC
Figure 2. 17510 Simplified Internal Block Diagram
19 PGND2
17510
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Analog Integrated Circuit Device Data Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
OUT1 LGND CRES NC OUT1 PGND NC VM IN1 IN2 C1H C1L
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
GIN VDD NC VM NC PGND OUT2 OUT2 EN GOUT C2H C2L
Figure 3. 17510 Pin Connections Table 1. 17510 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 8.
Pin Number 1, 5 2 3 4, 7, 20, 22 17, 18 6, 19 8, 21 9 10 11 12 13 14 15 16 23 24 Pin Name OUT1 LGND CRES NC OUT2 PGND VM IN1 IN2 C1H C1L C2L C2H GOUT EN VDD GIN Formal Name Output 1 Logic Ground Charge Pump Output Capacitor Connection No Connect Output 2 Power Ground Motor Drive Power Supply Input Control 1 Input Control 2 Charge Pump 1H Charge Pump 1L Charge Pump 2L Charge Pump 2H Gate Driver Output Enable Control Logic Supply Gate Driver Input Driver output 1 pins. Logic ground. Charge pump reservoir capacitor pin. No connection to these pins. Driver output 2 pins. Power ground. Motor power supply voltage input pins. Control signal input 1 pin. Control signal input 2 pin. Charge pump bucket capacitor 1 (positive pole). Charge pump bucket capacitor 1 (negative pole). Charge pump bucket capacitor 2 (negative pole). Charge pump bucket capacitor 2 (positive pole). Output gate driver signal to external MOSFET switch. Enable control signal input pin. Control circuit power supply pin. LOW = True control signal for GOUT pin. Definition
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings Motor Supply Voltage Charge Pump Output Voltage Logic Supply Voltage Signal Input Voltage (EN, IN1, IN2, GIN) Driver Output Current Continuous Peak (2) ESD Voltage
(3) (1)
Symbol VM
VCRES
Value - 0.5 - - 16 -0.5 to 13 -0.5 to 16 -0.5 to VDD + 0.5 1.2 3.8
Unit V V V V A
VDD VIN IO IOPK
V VESD1 VESD2 TSTG TJ TA PD RJA
(5)
Human Body Model Machine Model Storage Temperature Operating Junction Temperature Operating Ambient Temperature Power Dissipation
(4)
1900 130 -65 to 150 -30 to 150 -30 to 65 1.0 120 260 C C C W C/W C
Thermal Resistance Soldering Temperature
TSOLDER
Notes 1. When supplied externally, connect via 3.0 k resistor. 2. TA = 25C, 10 ms pulse at 200 ms interval. 3. 4. 5. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). TA = 25C, RJA = 120C/W, 37 mm x 50 mm Cu area (1.6 mm FR-4 PCB). Soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions TA = 25C, VM = 15 V, VDD = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic POWER Motor Supply Voltage Logic Supply Voltage Capacitor for Charge Pump Standby Power Supply Current (6) Motor Supply Standby Current Logic Supply Standby Current Logic Supply Current (7) Low-Voltage Detection Circuit Detection Voltage (VDD) Detection Voltage (VM) Driver Output ON Resistance (9) VM = 2.0 V, 8.0 V, 15 V GATE DRIVE Gate Drive Voltage (10) No Current Load Gate Drive Ability (Internally Supplied) I CRES = -1.0 mA
(8)
Symbol
Min
Typ
Max
Unit
VM VDD C1, C2, C3 I I
2.0 4.0 0.001
- - -
15 5.5 0.1
V V F A mA mA V
VMSTBY
- - -
- 0.3 3.3
1.0 1.0 4.0
VDDSTBY
I VDD
VDDDET VMDET RDS(ON)
1.5 4.0
2.5 5.0
3.5 6.0
- 0.45 0.55
VCRES
12 13 13.5
V
VCRESLOAD
10 11.2 -
V
Gate Drive Output IOUT = -50 A IIN = 50 A CONTROL LOGIC Logic Input Voltage (EN, IN1, IN2, GIN) Logic Input Function (4.0 V < VDD < 5.5 V) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current EN / GIN Pin Notes 6. Excluding pull-up resistor current, including current of gate-drive circuit. 7. fIN = 100 kHz. 8. 9. 10. VIH VIL IIH IIL IIL VDD x 0.7 - - -1.0 - 200 - - - - - 50 - VDD x 0.3 1.0 - - VIN 0 - VGOUTHIGH VGOUTLOW V CRES 0.5 LGND V CRES 0.1 LGND + 0.1 V CRES LGND +0.5
V
VDD
V
V V A A A
Detection voltage is defined as when the output becomes high-impedance after VDD drops below the detection threshold. When the gate voltage VCRES is applied from an external source, VCRES = 7.5 V. IO = 1.2 A source + sink. Input logic signal not present.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions TA = 25C, VM = 15 V, VDD = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic INPUT (EN, IN1, IN2, GIN) Pulse Input Frequency Input Pulse Rise Time
(11)
Symbol
Min
Typ
Max
Unit
fIN tR tF
- - -
- - -
200 1.0
(12)
kHz s s
Input Pulse Fall Time (13) OUTPUT Propagation Delay Time Turn-ON Time Turn-ON Time Turn-OFF Time GOUT Output Delay Time Turn-ON Time Turn-OFF Time Charge Pump Circuit Oscillator Frequency Rise Time (15) Low-Voltage Detection Time Notes 11. 12. 13. 14. 15.
(14)
1.0
(12)
s tPZH tPLH tPHL - - - 0.3 1.2 0.5 1.0 2.0 1.0 s tTON tTOFF - - - - 10 10
tV
fOSC
100 - -
200 0.1 -
400 1.0 10
kHz ms ms
CRESON
tVDDDET
Time is defined between 10% and 90%. That is, the input waveform slope must be steeper than this. Time is defined between 90% and 10%. Load is 500 pF. Time to charge CRES to 11 V after application of VDD.
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
TIMING DIAGRAMS
IN1, IN2, EN (GIN) tPZH*, tPLH (tTON)
50% VDD
VDDDETON
3.5 V 50%
VDDDETOFF
(tTOFF)
tPHL
1.5 V
t
VDDDET
tV
90%
90% OUTn (GOUT) 10% IM
DDDET
0% (<1.0 A)
* The last state is "Z". Figure 4. tPLH, tPHL, and tPZH Timing Table 5. Truth Table
INPUT EN H H H H L H H IN1 L H L H X X X IN2 L L H H X X X GIN X X X X X L H OUT1 Z H L L L X X OUTPUT OUT2 Z L H L L X X GOUT X X X X L H L
Figure 5. Low-Voltage Detection Timing
H = High. L = Low. Z = High impedance. X = Don't care. The GIN pin and EN pin are pulled up to VDD with internal resistance.
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 17510 is a monolithic H-Bridge power IC applicable to small DC motors used in portable electronics. The 17510 can operate efficiently with supply voltages as low as 2.0 V to as high as 15 V, and it can provide continuos motor drive currents of 1.2 A while handling peak currents up to 3.8 A. It is easily interfaced to low-cost MCUs via parallel 5.0 Vcompatible logic. The device can be pulse width modulated (PWM-ed) at up to 200 kHz. The 17510 has four operating modes: Forward, Reverse, Brake, and Tri-Stated (High Impedance). Basic protection and operational features (direction, dynamic braking, PWM control of speed and torque, main power supply undervoltage detection and shutdown, logic power supply undervoltage detection and shutdown), in addition to the 1.0 A rms output current capability, make the 17510 a very attractive, cost-effective solution for controlling a broad range of small DC motors. In addition, a pair of 17510 devices can be used to control bipolar stepper motors. The 17510 can also be used to excite transformer primary windings with a switched square wave to produce secondary winding AC currents. As shown in Figure 2, 17510 Simplified Internal Block Diagram, page 2, the 17510 is a monolithic H-Bridge with built-in charge pump circuitry. For a DC motor to run, the input conditions need to be set as follows: ENable input logic HIGH, one INput logic LOW, and the other INput logic HIGH (to define output polarity). The 17510 can execute dynamic braking by setting both IN1 and IN2 logic HIGH, causing both low-side MOSFETs in the output H-Bridge to turn ON. Dynamic braking can also implemented by taking the ENable logic LOW. The output of the H-Bridge can be set to an opencircuit high-impedance (Z) condition by taking both IN1 and IN2 logic LOW. (refer to Table 5, Truth Table, page 7). The 17510 outputs are capable of providing a continuous DC load current of up to 1.2 A. An internal charge pump supports PWM frequencies to 200 kHz. The EN pin also controls the charge pump, turning it off when EN = LOW, thus allowing the 17510 to be placed in a power-conserving sleep mode.
FUNCTIONAL PIN DESCRIPTION OUTPUT 1 AND OUTPUT2 (OUT1, OUT2)
The OUT1 and OUT2 pins provide the connection to the internal power MOSFET H-Bridge of the IC. A typical load connected between these pins would be a small DC motor. These outputs will connect to either VM or PGND, depending on the states of the control inputs (refer to Table 5, Truth Table, page 7).
MOTOR SUPPLY VOLTAGE INPUT (VM)
The VM pins carry the main supply voltage and current into the power sections of the IC. This supply then becomes controlled and/or modulated by the IC as it delivers the power to the load attached between OUT1 and OUT2. All VM pins must be connected together on the printed circuit board with as short as possible traces offering as low impedance as possible between pins. VM has an undervoltage threshold. If the supply voltage drops below the undervoltage threshold, the output power stage switches to a tri-state condition. When the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input pins.
POWER GROUND AND LOGIC GROUND (PGND, LGND)
The power and logic ground pins (PGND and LGND) should be connected together with a very low-impedance connection.
CHARGE PUMP RESERVOIR CAPACITOR (CRES)
The CRES pin provides the connection for the external reservoir capacitor (output of the charge pump). Alternatively this pin can also be used as an input to supply gate-drive voltage from an external source via a series current-limiting resistor. The voltage at the CRES pin will be approximately three times the VDD voltage, as the internal charge pump utilizes a voltage tripler circuit. The VCRES voltage is used by the IC to supply gate drive for the internal power MOSFET H-Bridge.
CONTROL SIGNAL INPUT AND ENABLE CONTROL SIGNAL INPUT (IN1, IN2, EN)
The IN1, IN2, and EN pins are input control pins used to control the outputs. These pins are 5.0 V CMOS-compatible inputs with hysteresis. The IN1, IN2, and EN work together to control OUT1 and OUT2 (refer to Table 5, Truth Table).
GATE DRIVER INPUT (GIN)
The GIN input controls the GOUT pin. When GIN is set logic LOW, GOUT supplies a level-shifted high-side gate drive signal to an external MOSFET. When GIN is set logic HIGH, GOUT is set to GND potential.
17510
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
CHARGE PUMP BUCKET CAPACITOR (C1L, C1H, C2L, C2H)
These two pairs of pins, the C1L and C1H and the C2L and C2H, connect to the external bucket capacitors required by the internal charge pump. The typical value for the bucket capacitors is 0.1 F.
CONTROL CIRCUIT POWER SUPPLY (VDD)
The VDD pin carries the 5.0 V supply voltage and current into the logic sections of the IC. VDD has an undervoltage threshold. If the supply voltage drops below the undervoltage threshold, the output power stage switches to a tri-state condition. When the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input pins.
GATE DRIVER OUTPUT (GOUT)
The GOUT output pin provides a level-shifted, high-side gate drive signal to an external MOSFET with CISS up to 500 pF.
17510
Analog Integrated Circuit Device Data Freescale Semiconductor
9
TYPICAL APPLICATIONS FUNCTIONAL PIN DESCRIPTION
TYPICAL APPLICATIONS
Figure 6 shows a typical application for the 17510.
5.0 V
17510 VDD VM GOUT
C1L C1H C2L C2H CRES
EN GIN IN1 IN2 GND
OUT1
Motor Solenoid
OUT2
MCU
Figure 6. 17510 Typical Application Diagram
CEMF SNUBBING TECHNIQUES
Care must be taken to protect the IC from potentially damaging CEMF spikes induced when commutating currents in inductive loads. Typical practice is to provide snubbing of voltage transients by placing a capacitor or zener at the supply pin (VM) (see Figure 7).
5.0 V 15 V 17510 VM VDD C1L C1H OUT1 C2L C2H CRES
OUT2
5.0 V 15 V 17510 VM VDD C1L C1H OUT1 C2L C2H CRES
OUT2
GND
GND
Figure 7. CEMF Snubbing Techniques
17510
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Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the "98A" listed below.
MTB SUFFIX EJ SUFFIX (PB-FREE) 24-PIN PLASTIC PACKAGE 98ASH70455A ISSUE B
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Analog Integrated Circuit Device Data Freescale Semiconductor
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PACKAGING PACKAGE DIMENSIONS (CONTINUED)
PACKAGE DIMENSIONS (continued)
MTB SUFFIX EJ SUFFIX (PB-FREE) 24-PIN PLASTIC PACKAGE 98ASH70455A ISSUE B
17510
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Analog Integrated Circuit Device Data Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION 2.0
DATE 7/2006
DESCRIPTION OF CHANGES
* Implemented a Revision History page. * Converted to Freescale format, and updated to the prevaiing form and style * Added EJ Pb-FREE package * Corrected symbol in Table 3, Driver Output ON Resistance from "W" to ""
3.0
1/2007
17510
Analog Integrated Circuit Device Data Freescale Semiconductor
13
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MPC17510 Rev. 3.0 1/2007

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